RTL Design Engineer

Responsibilities: The engineer will own the full micro-architecture and RTL design lifecycle for complex digital blocks. Responsibilities include implementing control logic, managing IP integration, and supporting design sign-off activities.

Requirements: Candidates must have strong expertise in SystemVerilog and recent experience designing custom RTL blocks and memory controllers. The role requires the ability to operate independently from day one with a solid understanding of SoC integration and sign-off flows.

Key skills: SystemVerilog, Verilog, RTL Design, Micro-architecture, Memory Controller Design, SoC Integration, CDC, RDC, Lint, Synthesis, IP Integration, DMA, SoC Bus Bridges, HBM, DDR4, DDR5

Keywords: RTL Design, SystemVerilog, Verilog, Micro-architecture, Custom Silicon, Memory Controllers, HBM, DDR4, DDR5, SoC Integration, CDC, RDC, Lint, Synthesis, DMA, Bus Bridges, IP Integration, Digital Subsystem, Die-to-Die, D2D, Hyperscaler, Digital Blocks, Control Logic